FPGA Developers wanted for leading market maker to join their fast-paced, dynamic engineering team. This role offers the opportunity to work on the research, design and implementation of FPGA solutions for their ultra-low-latency trading systems.
In this role, your main focus will be designing and deploying the proprietary hardware trading systems from concept to production. You'll also partner with technologists and traders design ultra low latency, high throughput, FPGA-based custom financial trading systems to accelerate algorithmic trade signal generation and order execution.
The FPGA team is small and highly experienced. They're constantly driving to identify ways to become more productive, and are seeking strong, analytical problem-solvers who can help build the next generation of cutting-edge, ultra-low-latency hardware solutions.
Requirements
Minimum 2 years' experience in the full ASIC or FPGA design lifecycle, including hardware architecture, RTL coding, simulation, verification, system integration, and testing.
Experience working in Verilog, System Verilog, and either Python or C++.
Strong working knowledge of FPGA design flow or physical design.
Ability to work in a Linux environment.
Minimum Bachelors degree in Computer Engineering, Computer Science, or related.
Financial experience is not required.
Rewards and Incentives
Hugely collaborative environment between teams, not siloed like other firms
Competitive compensation: truly flat structure; feel valued for your input and be rewarded for great ideas
Work with the latest technologies on complex problems
Flexible working encouraged and regular socials
Contact If you feel you are suitable for this role, or would like more information, drop me an email:
Jack Peck [e] jack.peck@oxfordknight.co.uk [t] +44 20 3745 6537 linkedin.com/in/jack-peck-448a70131